In general, the manufacturing process of semiconductor IC chips can be grouped into two major parts: the wafer fabrication process, which involves preparing a semiconductor wafer containing multiple identical integrated circuits, and the assembly and testing process, which involves machining the semiconductor wafer into semiconductor products of a desired form. The dicing is one of the steps of the assembly and testing process, in which a semiconductor wafer containing multiple identical integrated circuits is cut into individual semiconductor IC chips. Each individual semiconductor IC chip obtained by the dicing is packaged into a desired package or mounted on a desired substrate (for example, a glass substrate of a display panel and a printed circuit board) by a surface mount technology.
In general, the dicing is achieved by cutting a semiconductor wafer with a dicing blade. A region used as a reserve for cutting a semiconductor wafer with a dicing blade is often referred to as scribe region (also referred to as dicing lane or scribe lane).
One or more TEGs (test element groups) are often integrated in a scribe region. A TEG include various test elements (for example, MOS transistor and resistor elements) and electrical characteristics of the test elements are measured in the manufacturing process of semiconductor IC chips. The measured electrical characteristics are used for the management of the manufacturing process, for example.
The electrical connection to a test element included in a TEG is achieved by using an external connection pad (hereinafter, referred to as “TEG pad”) integrated in the scribe region. An electrical connection between a test element and a measuring device is established by placing a measurement probe on the TEG pad connected to the test element. TEGs (including TEG pads) integrated within a scribe region are broken and removed when the semiconductor wafer is cut with a dicing blade.
In recent semiconductor IC chips, mechanically weak films (for example, a low-permittivity dielectric film such as an organic silica glass film) are often used, and this undesirably increases surface chipping in the dicing. The occurrence of surface chipping undesirably reduces the yield of semiconductor IC chips and it is therefore desired to suppress the occurrence of surface chipping.
A structure in which a groove (or slit) is disposed along a guard ring (also referred to as “seal ring”) in the scribe region has been proposed as a technique for suppressing the occurrence of surface chipping. Such structures are disclosed in, for example, Japanese Patent Application Publications Nos. 2006-140404 A and 2007-049066 A.